Computational image and video processing is very demanding in terms of memory bandwidth as image resolutions and frame rates are high, with aggregate pixel rates in the high hundreds of megapixels per second being common place. Furthermore, as this field is in its relative infancy, algorithms are in constant flux. Therefore, it is difficult to implement them entirely in hardware as changes to the algorithms can mean hardware is unable to adapt. At the same time, a software approach relying on implementation in processors alone is unrealistic. Accordingly, it is generally desirable to provide a flexible architecture/infrastructure, which can accommodate processors and hardware accelerators.
At the same time, the demand for such video and image processing is coming to a large extent from portable electronic devices, for example tablet computers and mobile devices, where power consumption is a key consideration. As a result, there is a general need for a flexible infrastructure to couple programmable multicore processors and hardware accelerators with a high bandwidth memory subsystem that allows them to deliver a sustained data transfer rate at low power levels necessary for portable electronic devices.